1. Field of the Invention
The present invention relates to a method of manufacturing a capacitor having a pillar-like lower electrode.
2. Description of the Background Art
Increasing the degree of integration of semiconductor devices containing DRAMs (Dynamic Random Access Memories), or DRAMs and logic devices in combination, reduces the capacitor area for DRAMs, leading to a reduction in the capacitance of capacitors. In order to compensate for the reduction of capacitance, the dielectric material conventionally used as the capacitor dielectric films, i.e. the stacked structure of silicon oxide film (SiO) and silicon nitride film (SiN), is now being rapidly displaced by metal oxide dielectrics having larger relative permittivity, such as dielectrics with perovskite structure or tantalum oxide.
In this case, the lower electrodes of capacitors are exposed to a high-temperature oxidizing atmosphere during formation of the dielectric film. When the lower electrodes are oxidized by this, an oxide having a lower relative permittivity than the dielectric film is formed at the interface between the lower electrodes and the dielectric film. This greatly reduces the advantage of use of the high-dielectric-constant material as the dielectric film.
Accordingly, usually, noble metals of the platinum group such as Pt (platinum), Ru (ruthenium) and Ir (iridium), which are hereinafter referred to as platinum-group metals, are adopted as the material of the lower electrodes; the platinum-group metals are less susceptible to oxidation even when exposed to high-temperature oxidizing atmosphere, or they form conductive oxides even if oxidized. This avoids the formation of adversely affecting oxides of low dielectric constants at the interface between the lower electrodes and the dielectric film.
FIGS. 26 to 30 are cross-sectional views sequentially showing a capacitor manufacturing method according to a first conventional technique, where a metal oxide having a high dielectric constant is used as the material of the dielectric film and a platinum-group metal is used as the material of the lower electrodes. Now, referring to FIGS. 26 to 30, the first conventional capacitor manufacturing method is described.
As shown in FIG. 26, an interlayer insulating film 101 is provided which has contact plugs 102 formed therein. The top surfaces of the contact plugs 102 are exposed from the interlayer insulating film 101. Then an insulating film 107 is formed on the interlayer insulating film 101 and the contact plugs 102. The insulating film 107 includes a stopper film 103, an interlayer insulating film 104, a stopper film 105, and an interlayer insulating film 106, which are stacked in the order named. The insulating film 107 is formed so that the stopper film 103 is located on the side of the interlayer insulating film 101.
Next, the insulating film 107 is etched from the top surface to form holes 108 in the insulating film 107; the holes 108 reach the contact plugs 102. Though not shown, a semiconductor substrate having semiconductor elements connected to the contact plugs 102 resides under the interlayer insulating film 101 (i.e. on the side opposite to the insulating film 107).
Next, as shown in FIG. 27, by CVD (Chemical Vapor Deposition) method or plating method, an electrode material 109 of the lower electrodes is formed to fill the holes 108 and also formed on the top surface of the insulating film 107. The electrode material 109 is Ru, for example.
Then, as shown in FIG. 28, the structure obtained by the process of FIG. 27 is polished from the top surface thereof by, e.g. CMP (Chemical Mechanical Polishing) method, so as to remove the part of the electrode material 109 that is located above the holes 108. In this manner, lower electrodes 110 of Ru are formed filling the holes 108. Then, as shown in FIG. 29, part of the insulating film 107, more specifically the interlayer insulating film 106, is selectively removed by, e.g. wet etching. During this process, the stopper film 105 serves as an etching stopper.
Next, as shown in FIG. 30, a dielectric film 111 of, e.g. BST (barium strontium titanate: BaXSr(1xe2x88x92x)TiO3) having perovskite structure, is formed by CVD method on the lower electrodes 110 and the insulating film 107. Then an upper electrode 112 of, e.g. Ru, is formed on the dielectric film 111 to complete the capacitors.
As shown above, a metal oxide having a high dielectric constant is adopted as the material of the dielectric film 111 and a platinum-group metal is adopted as the material of the lower electrodes 110, and then it is possible to compensate for the reduction of capacitance that is caused as the semiconductor devices, like DRAMs, are more highly integrated. Capacitors that use a metal material as the upper and lower electrodes are called MIM capacitors.
In the first conventional capacitor manufacturing method, during the formation of the dielectric film 111 on the lower electrodes 110, the catalysis of the platinum-group metal, adopted as the material of the lower electrodes 110, may cause abnormalities in composition and shape of the dielectric film 111, which may degrade the electric characteristics of the capacitors.
Generally, the platinum-group metals produce strong catalysis on the surface in an oxidizing organic chemical reaction system. Now, the CVD method for forming the dielectric film 111 of a metal oxide having a high dielectric constant, like BST, is usually MOCVD (Metal Organic CVD) method that uses organic metal material gas and causes oxidation reaction; the platinum-group metal therefore exerts strong catalysis on the surface of the lower electrodes 110 during the formation of the dielectric film 111 on the lower electrodes 110. This strong catalysis may cause abnormalities in the composition and shape of the dielectric film 111.
FIG. 31 shows a condition in which the catalysis of the platinum-group metal changes the composition of the dielectric film 111 near the surface of the lower electrode 110; FIG. 31 shows the part A of FIG. 30 in an enlarged manner. The dielectric film 111a shown in FIG. 31 is formed during the early stages of the process of forming the dielectric film 111; the composition of the dielectric film 111a is made abnormal by the catalysis produced on the surface of the lower electrode 110. On the other hand, as the process of forming the dielectric film 111 advances, the dielectric film 111b shown in FIG. 31 is formed after the lower electrode 110 has been coated by the dielectric film 111a. Therefore it is not affected by the catalysis caused on the surface of the lower electrode 110 and therefore has a normal composition.
As shown above, the composition of the dielectric film 111a near the surface of the lower electrode 110 often considerably differs from that of the dielectric film 111b formed later and having normal composition. For example, when BST is used as the material of the dielectric film 111, the dielectric films 111a and 111b may exhibit considerably different composition ratios from each between the metallic elements of BST, more specifically between Ba or Sr and Ti.
Also, as shown in FIG. 32, the catalysis caused on the surface of the lower electrodes 110 may form abnormal projections in part of the dielectric film 111. FIG. 32 shows the capacitor structure where the upper electrode 112 is not formed yet.
In order to avoid these problems, a second conventional technique is suggested in which, in the formation of the dielectric film, part of the dielectric film is formed on the lower electrodes 110 by PVD (Physical Vapor Deposition) method and then the remaining part of the dielectric film is formed by CVD method on the dielectric film formed by PVD method.
FIG. 33 is a cross-sectional view showing a capacitor structure manufactured by the second conventional manufacturing method; FIG. 33 shows the capacitor structure where the upper electrode is not formed yet. As shown in FIG. 33, a dielectric film 120 including dielectric films 120a and 120b is formed on the lower electrodes 110; the dielectric film 120a is formed by PVD method on the lower electrodes 110 and then the dielectric film 120b is formed by CVD method on the dielectric film 120a formed by PVD method.
Unlike the CVD method, the PVD method is a physical film formation method that involves almost no chemical reaction, and therefore forming the dielectric film 120a by PVD method on the lower electrodes 110 can prevent occurrence of catalysis of the lower electrodes 110. Even when the dielectric film 120b formed by CVD method is made of the same kind of material as the dielectric film 120a, the catalysis of the lower electrodes 110 is not caused since the surfaces of the lower electrodes 110 are covered by the dielectric film 120a. Thus the dielectric film 120 suffers no abnormality in the composition and shape and hence no deterioration of capacitor electric characteristics.
However, because PVD method has poorer step coverage than CVD method, the second conventional method using PVD method may form the dielectric film 120a with insufficient thickness, as shown in the part B in FIG. 33. Therefore the second conventional method encounters difficulty in forming lower electrodes 110 having a high aspect ratio.
An object of the present invention is to provide a method for manufacturing a capacitor which can form a lower electrode having a high aspect ratio without suffering deterioration of the capacitor electric characteristics even when a platinum-group metal is adopted as the material of the lower electrode and a metal oxide having a high dielectric constant is adopted as the material of the dielectric film.
The present invention is directed to a capacitor manufacturing method including the steps (a) to (i). The step (a) is to provide an object to be connected. The step (b) is to form an insulating film on the object to be connected. The step (c) is to form a first hole in the insulating film. The step (d) is to form a first dielectric film on the surface of the first hole, without filling the first hole. The step (e) is to form a part of a lower electrode on the first dielectric film, without filling the first hole. The step (f) is to etch the structure obtained by the step (e) from above the surface of the part of the lower electrode that is formed on the bottom of the first hole, so as to form a second hole reaching the object to be connected in the structure obtained by the step (e). The step (g) is to form the remaining part of the lower electrode to fill the first and second holes. The step (h) to remove the insulating film after the step (g). The step (i) it to form an upper electrode on the first dielectric film after the step (h).
Since the first dielectric film is formed prior to the formation of the lower electrode, the lower electrode exert no catalysis even when a platinum-group metal is adopted as the material of the lower electrode and a metal oxide having a high dielectric constant is adopted as the material of the first dielectric film. As a result the capacitor can be manufactured without suffering deterioration of the electric characteristics.
Furthermore, since the first dielectric film is formed prior to the formation of the lower electrode, the first dielectric film can be formed by CVD method. Accordingly, as compared with ones formed by PVD method, the first dielectric film can be formed to a sufficient thickness on the surface of a hole having a high aspect ratio. This method can therefore be applied to the formation of lower electrodes having a high aspect ratio.
Moreover, during the formation of the second hole in the step (f), the structure is etched from above the surface of the part of the lower electrode, so that the first dielectric film is not damaged by the etching. Therefore the electric characteristics of the first dielectric film are not deteriorated in the step (f). This enhances the electric characteristics of the capacitor.